1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication method thereof, particularly to a semiconductor device and a fabrication method thereof in a form called System in Package (SiP) in which chips are packaged at the wafer level.
2. Description of the Related Art
There is an increasing demand for the realization of small-sized, low-profile, and light-weight portable electronics appliances such as a digital video camera, a digital cellular telephone, or a notebook personal computer. In order to respond to this demand, in one hand, 70% of reduction is realized in miniaturization of semiconductor devices such as recent VLSI. On the other hand, for an electronic circuit device in which such semiconductor devices are mounted on a printed wiring board, study and development have been conducted for, as an important challenge, how the packaging density of components on a substrate (printed wiring board) is improved.
For example, for the packaging form of the semiconductor device, the form is shifted from the lead insertion type such as DIP (Dual Inline Package) to the surface mounting type. Moreover, flip chip mounting is developed in which a bump (projected electrode) formed of solder or gold is disposed on a pad electrode of a semiconductor chip and the chip is connected to a wiring board through the bump as it is placed face down.
Moreover, now a package in a complex form is being developed which is called System in Package (SiP) in which in an insulating layer which insulates a rewiring layer formed on a semiconductor substrate (chip), a semiconductor chip having electronic circuits including an active device therein and passive devices such as a capacitance device and a coil are buried for packaging at the wafer level.
The configuration and the fabrication method of SiP are disclosed in Patent References 1 to 3, for example.
For a fabrication method of the wafer level SiP in which the semiconductor chip having the active device is buried in the insulating layer, for example, a semiconductor chip is mounted on a substrate, the semiconductor chip is buried with a photosensitive resin by spin coating or printing to form an insulating layer, the acquired insulating layer is patterned by exposure and development to form an opening for a pad electrode of the semiconductor chip, a conductive layer is buried in the opening by plating, and then a rewiring layer is formed.
In the fabrication method of SiP, in the process step of forming the insulating layer formed of the resin having the semiconductor chip buried therein, a high viscous resin is necessary in order to form an insulating layer having a thickness of 50 μm or greater. The film thickness made by a single spin coating is limited to 100 μm at the maximum. For example, when an insulating layer is formed thick in association with a semiconductor chip having a thickness of a few 100 μm, it is necessary that the layer is temporarily dried for every single coating to prevent the first coating from being dissolved in the process step for the second coating to secure the film thickness.
After the process step of burying the thick semiconductor chip with the resin insulating layer as described above, in the process step of exposure for patterning to form an opening for the pad electrode of the semiconductor chip, it is necessary to increase the amount of exposure depending on the film thickness of the resin insulating film to be exposed. Consequently, an increase in the amount of exposure causes a crush to a pattern, and it becomes difficult to conduct stable patterning.
Particularly, when a plurality of semiconductor chips having differences in the thickness is buried in a common resin insulating layer, the depth to the pad electrodes of the semiconductor chips differs. Thus, there is a problem that the focal depth differs in exposure and openings may not be formed in high resolution as the focus is adjusted to two pad electrodes. Therefore, by the method before, only semiconductor chips having the same thickness can be mounted.
Patent Reference 1: JP-A-2005-175402
Patent Reference 2: JP-A-2005-175320
Patent Reference 3: JP-A-2005-175319